hi

.gitignore

@@ -0,0 +1 @@
+/build/*

README.MD

@@ -0,0 +1,3 @@
+## Dependencies
+- verilator
+- clang++

makefile

@@ -0,0 +1,12 @@
+VERILATOR ?= verilator
+
+VERILOG_SOURCES = \
+	src/system.sv \
+	src/parts/hart.sv
+
+.PHONY: build
+
+build: ${VERILOG_SOURCES} 
+	mkdir -p build/verilog
+	${VERILATOR} --build --binary src/system.sv -Mdir build/verilog +incdir+src
+	cp -f build/verilog/Vsystem build/cpu

src/parts/hart.sv

@@ -0,0 +1,26 @@
+// RISC-V CPU Hart
+module hart(clock);
+    input clock; // the clock. pretty important. 
+
+    always begin
+        // instruction fetch
+        @(posedge clock);
+        $display("== INSTRUCTION FETCH ==");
+
+        // instruction decode
+        @(posedge clock);
+        $display("== INSTRUCTION DECODE ==");
+
+        // get shit
+        @(posedge clock);
+        $display("== GET REGISTERS ==");
+
+        // execute
+        @(posedge clock);
+        $display("== EXECUTE ==");
+
+        // write back
+        @(posedge clock);
+        $display("== WRITE REGISTERS ==");
+    end
+endmodule

src/system.sv

@@ -0,0 +1,10 @@
+`include "parts/hart.sv";
+
+module system();
+    reg clock = 0; // its the clock
+
+    hart core(clock); // cpu thing
+
+    // run the clock
+    always #1 clock = ~clock;
+endmodule;