commit 03803dd0019e15dce3002b49316caeceb1017b5e
Author: xwashere <xwashere0@protonmail.com>
Date:   Wed Dec 27 17:34:12 2023 -0500

    hi

diff --git a/.gitignore b/.gitignore
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+++ b/.gitignore
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+/build/*
diff --git a/README.MD b/README.MD
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+++ b/README.MD
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+## Dependencies
+- verilator
+- clang++
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diff --git a/makefile b/makefile
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+++ b/makefile
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+VERILATOR ?= verilator
+
+VERILOG_SOURCES = \
+	src/system.sv \
+	src/parts/hart.sv
+
+.PHONY: build
+
+build: ${VERILOG_SOURCES} 
+	mkdir -p build/verilog
+	${VERILATOR} --build --binary src/system.sv -Mdir build/verilog +incdir+src
+	cp -f build/verilog/Vsystem build/cpu
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diff --git a/src/parts/hart.sv b/src/parts/hart.sv
new file mode 100644
index 0000000..6e9c2d5
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+++ b/src/parts/hart.sv
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+// RISC-V CPU Hart
+module hart(clock);
+    input clock; // the clock. pretty important. 
+
+    always begin
+        // instruction fetch
+        @(posedge clock);
+        $display("== INSTRUCTION FETCH ==");
+
+        // instruction decode
+        @(posedge clock);
+        $display("== INSTRUCTION DECODE ==");
+
+        // get shit
+        @(posedge clock);
+        $display("== GET REGISTERS ==");
+
+        // execute
+        @(posedge clock);
+        $display("== EXECUTE ==");
+
+        // write back
+        @(posedge clock);
+        $display("== WRITE REGISTERS ==");
+    end
+endmodule
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diff --git a/src/system.sv b/src/system.sv
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+++ b/src/system.sv
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+`include "parts/hart.sv";
+
+module system();
+    reg clock = 0; // its the clock
+
+    hart core(clock); // cpu thing
+
+    // run the clock
+    always #1 clock = ~clock;
+endmodule;
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