factorio-riscv/makefile

12 lines
262 B
Makefile

VERILATOR ?= verilator
VERILOG_SOURCES = \
src/system.sv \
src/parts/hart.sv
.PHONY: build
build: ${VERILOG_SOURCES}
mkdir -p build/verilog
${VERILATOR} --build --binary src/system.sv -Mdir build/verilog +incdir+src
cp -f build/verilog/Vsystem build/cpu