hi
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commit
03803dd001
1
.gitignore
vendored
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1
.gitignore
vendored
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/build/*
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12
makefile
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12
makefile
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VERILATOR ?= verilator
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VERILOG_SOURCES = \
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src/system.sv \
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src/parts/hart.sv
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.PHONY: build
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build: ${VERILOG_SOURCES}
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mkdir -p build/verilog
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${VERILATOR} --build --binary src/system.sv -Mdir build/verilog +incdir+src
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cp -f build/verilog/Vsystem build/cpu
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26
src/parts/hart.sv
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26
src/parts/hart.sv
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// RISC-V CPU Hart
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module hart(clock);
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input clock; // the clock. pretty important.
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always begin
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// instruction fetch
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@(posedge clock);
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$display("== INSTRUCTION FETCH ==");
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// instruction decode
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@(posedge clock);
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$display("== INSTRUCTION DECODE ==");
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// get shit
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@(posedge clock);
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$display("== GET REGISTERS ==");
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// execute
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@(posedge clock);
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$display("== EXECUTE ==");
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// write back
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@(posedge clock);
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$display("== WRITE REGISTERS ==");
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end
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endmodule
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10
src/system.sv
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10
src/system.sv
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`include "parts/hart.sv";
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module system();
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reg clock = 0; // its the clock
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hart core(clock); // cpu thing
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// run the clock
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always #1 clock = ~clock;
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endmodule;
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