25 lines
638 B
Systemverilog
25 lines
638 B
Systemverilog
module ram(
|
|
input clk,
|
|
input reg rd,
|
|
input reg wr,
|
|
input reg[31:0] addr,
|
|
output reg[31:0] datar,
|
|
input reg[31:0] dataw
|
|
);
|
|
parameter SIZE = 'h1000;
|
|
|
|
reg [31:0] data[0 : SIZE - 1];
|
|
|
|
always @(posedge clk) begin
|
|
// $display("RAM: %c%c", wr ? "W" : "-", rd ? "R" : "-");
|
|
|
|
if (wr) begin
|
|
$display("RAM: [%08x] <= %d", addr << 2, dataw);
|
|
data[addr] = dataw;
|
|
end
|
|
if (rd) begin
|
|
$display("RAM: [%08x] => %d", addr << 2, data[addr]);
|
|
datar = data[addr];
|
|
end else datar = 0;
|
|
end
|
|
endmodule |