25 lines
638 B
Systemverilog
25 lines
638 B
Systemverilog
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module ram(
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input clk,
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input reg rd,
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input reg wr,
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input reg[31:0] addr,
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output reg[31:0] datar,
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input reg[31:0] dataw
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);
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parameter SIZE = 'h1000;
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reg [31:0] data[0 : SIZE - 1];
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always @(posedge clk) begin
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// $display("RAM: %c%c", wr ? "W" : "-", rd ? "R" : "-");
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if (wr) begin
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$display("RAM: [%08x] <= %d", addr << 2, dataw);
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data[addr] = dataw;
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end
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if (rd) begin
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$display("RAM: [%08x] => %d", addr << 2, data[addr]);
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datar = data[addr];
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end else datar = 0;
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end
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endmodule
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