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risc-v in factorio holy shit
6 Commits
1 Branch
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52 KiB
SystemVerilog 92.7%
Makefile 3.9%
Assembly 3.4%
 
 
 
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memory instructions 		2023-12-29 16:59:32 -05:00
board memory instructions 2023-12-29 16:59:32 -05:00
os/kernel memory instructions 2023-12-29 16:59:32 -05:00
.gitignore hi 2023-12-27 20:46:56 -05:00
README.MD all hart shit except doing things 2023-12-29 13:45:02 -05:00
makefile memory instructions 2023-12-29 16:59:32 -05:00

README.MD

Dependencies

  • verilator
  • clang (with risc-v support)