more shit

board/parts/hart.sv

@@ -0,0 +1,50 @@
+// RISC-V CPU Hart
+module hart(
+    clk,
+
+    pmmu_rd, pmmu_wr,
+    pmmu_addr, pmmu_datar, pmmu_dataw
+);
+    input clk; // the clock. pretty important. 
+
+    output reg        pmmu_rd;
+    output reg        pmmu_wr;
+    output reg [31:0] pmmu_addr;
+    input  reg [31:0] pmmu_datar;
+    output reg [31:0] pmmu_dataw;
+
+    reg [31:0] reg_pc = 0; 
+
+    reg [31:0] t_ins = 0; // 
+
+    always begin
+        // instruction fetch
+        @(posedge clk);
+        $display("== INSTRUCTION FETCH (0x%08h) ==", reg_pc);
+
+        pmmu_addr = reg_pc;
+        pmmu_rd   = 1;
+
+        // instruction decode
+        @(posedge clk);
+        $display("== INSTRUCTION DECODE (0x%08h) ==", pmmu_datar);
+        t_ins     = pmmu_datar;
+        pmmu_addr = 0;
+        pmmu_rd   = 1;
+
+        // get shit
+        @(posedge clk);
+        $display("== GET REGISTERS ==");
+
+        // execute
+        @(posedge clk);
+        $display("== EXECUTE ==");
+
+        // write back
+        @(posedge clk);
+        $display("== WRITE REGISTERS ==");
+
+        // finish up
+        reg_pc += 4;
+    end
+endmodule

board/parts/pmmu.sv

@@ -0,0 +1,40 @@
+module pmmu(
+    clk,
+    rd, wr,
+    addr, datar, dataw,
+
+    rom_rd, rom_wr,
+    rom_addr, rom_datar, rom_dataw
+);
+    // INPUT SHIT
+    input             clk;
+    input  reg        rd;
+    input  reg        wr;
+    input  reg [31:0] addr;
+    input  reg [31:0] dataw;
+    output reg [31:0] datar;
+
+    // ROM
+    output reg        rom_rd;
+    output reg        rom_wr;
+    output reg [31:0] rom_addr;
+    output reg [31:0] rom_dataw;
+    input  reg [31:0] rom_datar;
+
+    always @(posedge clk) begin
+        rom_rd = 0;
+        rom_wr = 0;
+
+        if ((addr == 0 || addr > 0) && addr < 'h10000) begin
+                    rom_addr  = addr;
+                    rom_wr    = wr;
+                    rom_rd    = rd;
+            if (wr) rom_dataw = dataw;
+
+            #1;
+            if (rd) datar = rom_datar;
+        end else begin
+            $error("THIS IS BAD");
+        end
+    end
+endmodule

board/parts/rom.sv

@@ -0,0 +1,30 @@
+// RISC-V Read only memory
+module rom(clk, rd, wr, addr, datar, dataw);
+    input             clk;
+    input  reg        rd;
+    input  reg        wr; // wait why the fuck did i add a write pin
+    input  reg [31:0] addr;
+    output reg [31:0] datar;
+    input  reg [31:0] dataw;
+
+    always @(posedge clk) begin
+        if (rd) begin
+            case (addr >> 2)
+                0:  datar = 0;
+                1:  datar = 1;
+                2:  datar = 2;
+                3:  datar = 3;
+                4:  datar = 4;
+                5:  datar = 5;
+                6:  datar = 6;
+                7:  datar = 7;
+                8:  datar = 8;
+                9:  datar = 9;
+                10: datar = 10;
+                default: $error("INVALID MEMORY ACCESS"); 
+            endcase
+        end else begin 
+            datar = 0;
+        end
+    end
+endmodule

board/system.sv

@@ -0,0 +1,27 @@
+`include "parts/hart.sv";
+`include "parts/pmmu.sv";
+`include "parts/rom.sv";
+
+module system();
+    reg clock = 0; // its the clock
+    
+    reg        wire_rd;
+    reg        wire_wr;
+    reg [31:0] wire_addr;
+    reg [31:0] wire_datar;
+    reg [31:0] wire_dataw;
+    reg        wire_rom_rd;
+    reg        wire_rom_wr;
+    reg [31:0] wire_rom_addr;
+    reg [31:0] wire_rom_datar;
+    reg [31:0] wire_rom_dataw;
+
+
+    hart core(clock, wire_rd, wire_wr, wire_addr, wire_datar, wire_dataw); // cpu thing
+    
+    rom  rom(clock, wire_rom_rd, wire_rom_wr, wire_rom_addr, wire_rom_datar, wire_rom_dataw);
+    pmmu pmmu(clock, wire_rd, wire_wr, wire_addr, wire_datar, wire_dataw, wire_rom_rd, wire_rom_wr, wire_rom_addr, wire_rom_datar, wire_rom_dataw);
+
+    // run the clock
+    always #5 clock = ~clock;
+endmodule;

makefile

@@ -1,12 +1,12 @@
 VERILATOR ?= verilator
 
 VERILOG_SOURCES = \
-	src/system.sv \
-	src/parts/hart.sv
+	board/system.sv \
+	board/parts/hart.sv \
+	board/parts/pmmu.sv \
+	board/parts/rom.sv 
 
-.PHONY: build
-
-build: ${VERILOG_SOURCES} 
+build/cpu: ${VERILOG_SOURCES} 
 	mkdir -p build/verilog
-	${VERILATOR} --build --binary src/system.sv -Mdir build/verilog +incdir+src
+	${VERILATOR} --build --binary board/system.sv -Mdir build/verilog +incdir+board
 	cp -f build/verilog/Vsystem build/cpu

src/parts/hart.sv

@@ -1,26 +0,0 @@
-// RISC-V CPU Hart
-module hart(clock);
-    input clock; // the clock. pretty important. 
-
-    always begin
-        // instruction fetch
-        @(posedge clock);
-        $display("== INSTRUCTION FETCH ==");
-
-        // instruction decode
-        @(posedge clock);
-        $display("== INSTRUCTION DECODE ==");
-
-        // get shit
-        @(posedge clock);
-        $display("== GET REGISTERS ==");
-
-        // execute
-        @(posedge clock);
-        $display("== EXECUTE ==");
-
-        // write back
-        @(posedge clock);
-        $display("== WRITE REGISTERS ==");
-    end
-endmodule

src/system.sv

@@ -1,10 +0,0 @@
-`include "parts/hart.sv";
-
-module system();
-    reg clock = 0; // its the clock
-
-    hart core(clock); // cpu thing
-
-    // run the clock
-    always #1 clock = ~clock;
-endmodule;