50 lines
1.1 KiB
Systemverilog
50 lines
1.1 KiB
Systemverilog
// RISC-V CPU Hart
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module hart(
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clk,
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pmmu_rd, pmmu_wr,
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pmmu_addr, pmmu_datar, pmmu_dataw
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);
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input clk; // the clock. pretty important.
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output reg pmmu_rd;
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output reg pmmu_wr;
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output reg [31:0] pmmu_addr;
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input reg [31:0] pmmu_datar;
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output reg [31:0] pmmu_dataw;
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reg [31:0] reg_pc = 0;
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reg [31:0] t_ins = 0; //
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always begin
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// instruction fetch
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@(posedge clk);
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$display("== INSTRUCTION FETCH (0x%08h) ==", reg_pc);
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pmmu_addr = reg_pc;
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pmmu_rd = 1;
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// instruction decode
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@(posedge clk);
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$display("== INSTRUCTION DECODE (0x%08h) ==", pmmu_datar);
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t_ins = pmmu_datar;
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pmmu_addr = 0;
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pmmu_rd = 1;
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// get shit
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@(posedge clk);
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$display("== GET REGISTERS ==");
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// execute
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@(posedge clk);
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$display("== EXECUTE ==");
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// write back
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@(posedge clk);
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$display("== WRITE REGISTERS ==");
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// finish up
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reg_pc += 4;
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end
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endmodule |