// RISC-V CPU Hart
module hart(
    clk,

    pmmu_rd, pmmu_wr,
    pmmu_addr, pmmu_datar, pmmu_dataw
);
    input clk; // the clock. pretty important. 

    output reg        pmmu_rd;
    output reg        pmmu_wr;
    output reg [31:0] pmmu_addr;
    input  reg [31:0] pmmu_datar;
    output reg [31:0] pmmu_dataw;

    reg [31:0] reg_pc = 0; 

    reg [31:0] t_ins = 0; // 

    always begin
        // instruction fetch
        @(posedge clk);
        $display("== INSTRUCTION FETCH (0x%08h) ==", reg_pc);

        pmmu_addr = reg_pc;
        pmmu_rd   = 1;

        // instruction decode
        @(posedge clk);
        $display("== INSTRUCTION DECODE (0x%08h) ==", pmmu_datar);
        t_ins     = pmmu_datar;
        pmmu_addr = 0;
        pmmu_rd   = 1;

        // get shit
        @(posedge clk);
        $display("== GET REGISTERS ==");

        // execute
        @(posedge clk);
        $display("== EXECUTE ==");

        // write back
        @(posedge clk);
        $display("== WRITE REGISTERS ==");

        // finish up
        reg_pc += 4;
    end
endmodule