factorio-riscv/makefile

VERILATOR ?= verilator

CC        ?= clang

VERILOG_SOURCES = \
	board/system.sv \
	board/parts/hart.sv \
	board/parts/pmmu.sv \
	board/parts/rom.sv \
	board/parts/ram.sv 

KERNEL_SOURCES = \
	os/kernel/boot.s

.PHONY: build

build: build/cpu build/kernel.mem

build/cpu: ${VERILOG_SOURCES}
	mkdir -p build/verilog
	${VERILATOR} --build --binary board/system.sv -Mdir build/verilog +incdir+board
	cp -f build/verilog/Vsystem build/cpu

build/kernel.mem: build/kernel
	hexdump build/kernel -e '1/4 "%x "' > build/kernel.mem

build/kernel: ${KERNEL_SOURCES}
	clang ${KERNEL_SOURCES} -o build/kernel \
		--target=riscv32 \
		-nostdlib \
		-march=rv32i \
		-Xlinker --oformat=binary