factorio-riscv/makefile

32 lines
678 B
Makefile
Raw Normal View History

2023-12-27 22:34:12 +00:00
VERILATOR ?= verilator
2023-12-29 14:13:28 +00:00
CC ?= clang
2023-12-27 22:34:12 +00:00
VERILOG_SOURCES = \
2023-12-29 14:10:10 +00:00
board/system.sv \
board/parts/hart.sv \
board/parts/pmmu.sv \
2023-12-29 21:59:32 +00:00
board/parts/rom.sv \
board/parts/ram.sv
2023-12-27 22:34:12 +00:00
2023-12-29 14:13:28 +00:00
KERNEL_SOURCES = \
os/kernel/boot.s
2023-12-29 18:45:02 +00:00
.PHONY: build
build: build/cpu build/kernel.mem
build/cpu: ${VERILOG_SOURCES}
2023-12-27 22:34:12 +00:00
mkdir -p build/verilog
2023-12-29 14:10:10 +00:00
${VERILATOR} --build --binary board/system.sv -Mdir build/verilog +incdir+board
2023-12-29 14:13:28 +00:00
cp -f build/verilog/Vsystem build/cpu
2023-12-29 18:45:02 +00:00
build/kernel.mem: build/kernel
hexdump build/kernel -e '1/4 "%x "' > build/kernel.mem
2023-12-29 14:13:28 +00:00
build/kernel: ${KERNEL_SOURCES}
2023-12-29 18:45:02 +00:00
clang ${KERNEL_SOURCES} -o build/kernel \
2023-12-29 20:00:02 +00:00
--target=riscv32 \
2023-12-29 18:45:02 +00:00
-nostdlib \
2023-12-29 20:00:02 +00:00
-march=rv32i \
2023-12-29 18:45:02 +00:00
-Xlinker --oformat=binary