24 lines
496 B
Systemverilog
24 lines
496 B
Systemverilog
// RISC-V Read only memory
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module rom(clk, rd, addr, datar);
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input clk;
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input reg rd;
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input reg [31:0] addr;
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output reg [31:0] datar;
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parameter SIZE = 'h100;
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parameter FILE = "";
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reg [31:0] data [0 : SIZE - 1];
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always @(posedge clk) begin
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if (rd) begin
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datar = data[addr];
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end else begin
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datar = 0;
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end
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end
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initial begin
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$readmemh(FILE, data, 0, SIZE - 1);
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end
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endmodule |