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factorio-riscv
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master
xwashere 2023-12-29 09:13:28 -05:00
parent f8a1baeee0
commit 1174a098c3
Signed by: XWasHere
GPG Key ID: 042F8BFA1B0EF93B
1 changed files with 9 additions and 1 deletions
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8
makefile
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@ -1,12 +1,20 @@
VERILATOR ?= verilator VERILATOR ?= verilator
CC ?= clang
VERILOG_SOURCES = \ VERILOG_SOURCES = \
board/system.sv \ board/system.sv \
board/parts/hart.sv \ board/parts/hart.sv \
board/parts/pmmu.sv \ board/parts/pmmu.sv \
board/parts/rom.sv board/parts/rom.sv
KERNEL_SOURCES = \
os/kernel/boot.s
build/cpu: ${VERILOG_SOURCES} build/cpu: ${VERILOG_SOURCES}
mkdir -p build/verilog mkdir -p build/verilog
${VERILATOR} --build --binary board/system.sv -Mdir build/verilog +incdir+board ${VERILATOR} --build --binary board/system.sv -Mdir build/verilog +incdir+board
cp -f build/verilog/Vsystem build/cpu cp -f build/verilog/Vsystem build/cpu
build/kernel: ${KERNEL_SOURCES}
clang ${KERNEL_SOURCES} -o build/kernel