factorio-riscv/makefile

20 lines
437 B
Makefile

VERILATOR ?= verilator
CC ?= clang
VERILOG_SOURCES = \
board/system.sv \
board/parts/hart.sv \
board/parts/pmmu.sv \
board/parts/rom.sv
KERNEL_SOURCES = \
os/kernel/boot.s
build/cpu: ${VERILOG_SOURCES}
mkdir -p build/verilog
${VERILATOR} --build --binary board/system.sv -Mdir build/verilog +incdir+board
cp -f build/verilog/Vsystem build/cpu
build/kernel: ${KERNEL_SOURCES}
clang ${KERNEL_SOURCES} -o build/kernel