factorio-riscv/board/parts/pmmu.sv

// System physical memory management unit, addresses are dword aligned
module pmmu(
    clk,
    rd, wr,
    addr, datar, dataw,

    rom_rd,
    rom_addr, rom_datar
);
    // INPUT SHIT
    input             clk;
    input  reg        rd;
    input  reg        wr;
    input  reg [31:0] addr;
    input  reg [31:0] dataw;
    output reg [31:0] datar;

    // ROM
    output reg        rom_rd;
    output reg [31:0] rom_addr;
    input  reg [31:0] rom_datar;

    always @(posedge clk) begin
        rom_rd = 0;

        if ((addr == 0 || addr > 0) && addr < 'h100) begin
                    rom_addr  = addr >> 2;
                    rom_rd    = rd;
            #1; // wait for it to finish
            if (rd) datar = rom_datar;
        end else begin
            $error("THIS IS BAD");
        end
    end
endmodule