40 lines
897 B
Systemverilog
40 lines
897 B
Systemverilog
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module pmmu(
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clk,
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rd, wr,
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addr, datar, dataw,
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rom_rd, rom_wr,
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rom_addr, rom_datar, rom_dataw
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);
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// INPUT SHIT
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input clk;
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input reg rd;
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input reg wr;
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input reg [31:0] addr;
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input reg [31:0] dataw;
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output reg [31:0] datar;
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// ROM
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output reg rom_rd;
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output reg rom_wr;
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output reg [31:0] rom_addr;
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output reg [31:0] rom_dataw;
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input reg [31:0] rom_datar;
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always @(posedge clk) begin
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rom_rd = 0;
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rom_wr = 0;
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if ((addr == 0 || addr > 0) && addr < 'h10000) begin
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rom_addr = addr;
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rom_wr = wr;
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rom_rd = rd;
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if (wr) rom_dataw = dataw;
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#1;
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if (rd) datar = rom_datar;
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end else begin
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$error("THIS IS BAD");
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end
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end
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endmodule
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