factorio-riscv/board/system.sv

`include "parts/hart.sv";
`include "parts/pmmu.sv";
`include "parts/rom.sv";
`include "parts/ram.sv";

module system();
    reg clock = 0; // its the clock
    
    reg        wire_rd;
    reg        wire_wr;
    reg [31:0] wire_addr;
    reg [31:0] wire_datar;
    reg [31:0] wire_dataw;
    reg        wire_rom_rd;
    reg [31:0] wire_rom_addr;
    reg [31:0] wire_rom_datar;
    reg        wire_ram_rd;
    reg        wire_ram_wr;
    reg [31:0] wire_ram_addr;
    reg [31:0] wire_ram_datar;
    reg [31:0] wire_ram_dataw;

    hart core(clock, wire_rd, wire_wr, wire_addr, wire_datar, wire_dataw); // cpu thing
    
    rom#(.FILE("./build/kernel.mem")) rom(clock, wire_rom_rd, wire_rom_addr, wire_rom_datar);
    ram#(.SIZE('h1000)) ram(clock, wire_ram_rd, wire_ram_wr, wire_ram_addr, wire_ram_datar, wire_ram_dataw);
    pmmu pmmu(clock, wire_rd, wire_wr, wire_addr, wire_datar, wire_dataw, wire_rom_rd, wire_rom_addr, wire_rom_datar, wire_ram_rd, wire_ram_wr, wire_ram_addr, wire_ram_datar, wire_ram_dataw);

    // run the clock
    always #5 clock = ~clock;
endmodule;