284 lines
9.2 KiB
Systemverilog
284 lines
9.2 KiB
Systemverilog
`define INS_LUI 7'b0110111
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`define INS_AUIPC 7'b0010111
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`define INS_JAL 7'b1101111
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`define INS_JALR 7'b1100111
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`define INS_BRANCH 7'b1100011
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`define INS_LOAD 7'b0000011
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`define INS_STORE 7'b0100011
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`define INS_IMMOP 7'b0010011
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`define INS_REGOP 7'b0110011
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`define INS_FENCE 7'b0001111
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`define INS_ENVOP 7'b1110011
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`define INS_BRANCH_EQ 3'b000
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`define INS_BRANCH_NE 3'b001
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`define INS_BRANCH_LT 3'b100
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`define INS_BRANCH_GE 3'b101
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`define INS_BRANCH_LTU 3'b110
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`define INS_BRANCH_GEU 3'b111
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`define INS_LOAD_8 3'b000
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`define INS_LOAD_16 3'b001
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`define INS_LOAD_32 3'b010
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`define INS_LOAD_U8 3'b100
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`define INS_LOAD_U16 3'b101
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`define INS_STORE_8 3'b000
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`define INS_STORE_16 3'b001
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`define INS_STORE_32 3'b010
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`define INS_ALUOP_ADD 3'b000
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`define INS_ALUOP_SLT 3'b010
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`define INS_ALUOP_SLTU 3'b011
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`define INS_ALUOP_XOR 3'b100
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`define INS_ALUOP_OR 3'b110
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`define INS_ALUOP_AND 3'b111
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`define INS_ALUOP_SLL 3'b001
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`define INS_ALUOP_SRL 3'b101
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`define INS_ENVOP_CALL 12'b000000000000
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`define INS_ENVOP_BREAK 12'b000000000001
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`define F3_DONT_CARE 3'b???
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`define F7_DONT_CARE 7'b???????
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// RISC-V CPU Hart
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module hart(
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clk,
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pmmu_rd, pmmu_wr,
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pmmu_addr, pmmu_datar, pmmu_dataw
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);
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input clk; // the clock. pretty important.
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output reg pmmu_rd;
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output reg pmmu_wr;
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output reg [31:0] pmmu_addr;
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input reg [31:0] pmmu_datar;
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output reg [31:0] pmmu_dataw;
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reg [31:0] reg_pc = 0;
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reg [31:0] reg_int [31:0];
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// FETCH DATA
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reg [31:0] t_ins = 0; // temp for being processed instruction
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// DECODE DATA
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reg [6:0] t_d_op;
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reg [4:0] t_d_rd;
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reg [2:0] t_d_f3;
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reg [4:0] t_d_r1;
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reg [4:0] t_d_r2;
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reg [6:0] t_d_f7;
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reg [31:0] t_d_immi;
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reg [31:0] t_d_imms;
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reg [31:0] t_d_immb;
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reg [31:0] t_d_immu;
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reg [31:0] t_d_immj;
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reg [31:0] t_d_imm;
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// GET REGISTERS
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reg [31:0] t_r_a;
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reg [31:0] t_r_b;
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// EXECUTE INSTRUCTION
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reg [31:0] t_e_result;
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reg t_e_branch;
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reg [31:0] t_e_address;
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always begin
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// instruction fetch
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@(posedge clk);
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$display("== INSTRUCTION FETCH (0x%08h) ==", reg_pc);
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pmmu_addr = reg_pc;
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pmmu_rd = 1;
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// instruction decode
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@(posedge clk);
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$display("== INSTRUCTION DECODE (0x%08h) ==", pmmu_datar);
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t_ins = pmmu_datar;
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pmmu_addr = 0;
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pmmu_rd = 0;
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t_d_op = t_ins[6:0];
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t_d_rd = t_ins[11:7];
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t_d_f3 = t_ins[14:12];
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t_d_r1 = t_ins[19:15];
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t_d_r2 = t_ins[24:20];
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t_d_f7 = t_ins[31:25];
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t_d_immi = {{21{t_ins[31]}}, t_ins[30:20] };
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t_d_imms = {{21{t_ins[31]}}, t_ins[30:25], t_ins[11:7] };
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t_d_immb = {{20{t_ins[31]}}, t_ins[7], t_ins[30:25], t_ins[11:8], 1'b0 };
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t_d_immu = { t_ins[31:12], 12'b0 };
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t_d_immj = {{12{t_ins[31]}}, t_ins[19:12], t_ins[20], t_ins[30:21], 1'b0 };
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case (t_d_op)
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`INS_JALR,
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`INS_LOAD,
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`INS_IMMOP: t_d_imm = t_d_immi;
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`INS_JAL: t_d_imm = t_d_immj;
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`INS_STORE: t_d_imm = t_d_imms;
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`INS_BRANCH: t_d_imm = t_d_immb;
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`INS_LUI,
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`INS_AUIPC: t_d_imm = t_d_immu;
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`INS_ENVOP,
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`INS_FENCE,
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`INS_REGOP: t_d_imm = 0;
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default: $error("INVALID INSTRUCTION %b", t_d_op);
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endcase
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$display("INS: %7b %3b %7b %d %d -> %d", t_d_op, t_d_f3, t_d_f7, t_d_r1, t_d_r2, t_d_rd);
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$display("IMM: U[%d] S[%d]", t_d_imm, $signed(t_d_imm));
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// get registers
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@(posedge clk);
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$display("== GET REGISTERS ==");
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t_r_a = reg_int[t_d_r1];
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t_r_b = reg_int[t_d_r2];
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$display("REG: %d[%d] %d[%d]", t_d_r1, t_r_a, t_d_r2, t_r_b);
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// execute
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@(posedge clk);
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$display("== EXECUTE ==");
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t_e_address = 0;
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t_e_branch = 0;
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t_e_result = 0;
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casez ({ t_d_op, t_d_f3, t_d_f7 })
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{ `INS_LUI, `F3_DONT_CARE, `F7_DONT_CARE }: t_e_result = t_d_imm;
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{ `INS_AUIPC, `F3_DONT_CARE, `F7_DONT_CARE }: t_e_result = t_d_imm + reg_pc;
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{ `INS_JAL, `F3_DONT_CARE, `F7_DONT_CARE }: begin
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t_e_result = reg_pc + 4;
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t_e_address = reg_pc + t_d_imm;
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t_e_branch = 1;
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end
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{ `INS_JALR, `F3_DONT_CARE, `F7_DONT_CARE }: begin
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t_e_result = reg_pc + 4;
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t_e_address = (t_r_a + t_d_imm) & ~1;
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t_e_branch = 1;
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end
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{ `INS_BRANCH, `INS_BRANCH_EQ, `F7_DONT_CARE }: begin
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if (t_r_a == t_r_b) begin
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t_e_address = reg_pc + t_d_imm;
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t_e_branch = 1;
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end
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end
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{ `INS_BRANCH, `INS_BRANCH_NE, `F7_DONT_CARE }: begin
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if (t_r_a != t_r_b) begin
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t_e_address = reg_pc + t_d_imm;
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t_e_branch = 1;
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end
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end
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{ `INS_BRANCH, `INS_BRANCH_LT, `F7_DONT_CARE }: begin
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if ($signed(t_r_a) < $signed(t_r_b)) begin
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t_e_address = reg_pc + t_d_imm;
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t_e_branch = 1;
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end
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end
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{ `INS_BRANCH, `INS_BRANCH_GE, `F7_DONT_CARE }: begin
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if ($signed(t_r_a) >= $signed(t_r_b)) begin
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t_e_address = reg_pc + t_d_imm;
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t_e_branch = 1;
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end
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end
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{ `INS_BRANCH, `INS_BRANCH_LTU, `F7_DONT_CARE }: begin
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if (t_r_a < t_r_b) begin
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t_e_address = reg_pc + t_d_imm;
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t_e_branch = 1;
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end
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end
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{ `INS_BRANCH, `INS_BRANCH_GEU, `F7_DONT_CARE }: begin
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if (t_r_a >= t_r_b) begin
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t_e_address = reg_pc + t_d_imm;
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t_e_branch = 1;
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end
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end
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{ `INS_LOAD, `F3_DONT_CARE, `F7_DONT_CARE }: $error("NOT IMPLEMENTED");
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{ `INS_STORE, `F3_DONT_CARE, `F7_DONT_CARE }: $error("NOT IMPLEMENTED");
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{ `INS_IMMOP, `INS_ALUOP_ADD, `F7_DONT_CARE }: begin
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t_e_result = $signed(t_r_a) + $signed(t_d_imm);
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end
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{ `INS_IMMOP, `INS_ALUOP_SLT, `F7_DONT_CARE }: begin
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t_e_result = $signed(t_r_a) < $signed(t_d_imm) ? 1 : 0;
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end
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{ `INS_IMMOP, `INS_ALUOP_SLTU, `F7_DONT_CARE }: begin
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t_e_result = t_r_a < t_d_imm ? 1 : 0;
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end
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{ `INS_IMMOP, `INS_ALUOP_XOR, `F7_DONT_CARE }: begin
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t_e_result = t_r_a ^ t_d_imm;
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end
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{ `INS_IMMOP, `INS_ALUOP_OR, `F7_DONT_CARE }: begin
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t_e_result = t_r_a | t_d_imm;
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end
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{ `INS_IMMOP, `INS_ALUOP_AND, `F7_DONT_CARE }: begin
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t_e_result = t_r_a & t_d_imm;
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end
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{ `INS_IMMOP, `INS_ALUOP_SLL, 7'b0000000 }: begin
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t_e_result = t_r_a << (t_d_imm & 31);
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end
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{ `INS_IMMOP, `INS_ALUOP_SRL, 7'b0000000 }: begin
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t_e_result = t_r_a >> (t_d_imm & 31);
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end
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{ `INS_IMMOP, `INS_ALUOP_SRL, 7'b0100000 }: begin
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t_e_result = t_r_a >>> (t_d_imm & 31);
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end
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{ `INS_REGOP, `INS_ALUOP_ADD, 7'b0000000 }: begin
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t_e_result = $signed(t_r_a) + $signed(t_r_b);
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end
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{ `INS_REGOP, `INS_ALUOP_ADD, 7'b0100000 }: begin
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t_e_result = $signed(t_r_a) - $signed(t_r_b);
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end
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{ `INS_REGOP, `INS_ALUOP_SLT, 7'b0000000 }: begin
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t_e_result = $signed(t_r_a) < $signed(t_r_b) ? 1 : 0;
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end
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{ `INS_REGOP, `INS_ALUOP_SLTU, 7'b0000000 }: begin
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t_e_result = t_r_a < t_r_b ? 1 : 0;
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end
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{ `INS_REGOP, `INS_ALUOP_XOR, 7'b0000000 }: begin
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t_e_result = t_r_a ^ t_r_b;
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end
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{ `INS_REGOP, `INS_ALUOP_OR, 7'b0000000 }: begin
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t_e_result = t_r_a | t_r_b;
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end
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{ `INS_REGOP, `INS_ALUOP_AND, 7'b0000000 }: begin
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t_e_result = t_r_a & t_r_b;
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end
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{ `INS_REGOP, `INS_ALUOP_SLL, 7'b0000000 }: begin
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t_e_result = t_r_a << (t_r_b & 31);
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end
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{ `INS_REGOP, `INS_ALUOP_SRL, 7'b0000000 }: begin
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t_e_result = t_r_a >> (t_r_b & 31);
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end
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{ `INS_REGOP, `INS_ALUOP_SRL, 7'b0100000 }: begin
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t_e_result = t_r_a >>> (t_r_b & 31);
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end
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{ `INS_FENCE, `F3_DONT_CARE, `F7_DONT_CARE }:;
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{ `INS_ENVOP, `F3_DONT_CARE, `F7_DONT_CARE }:;
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default: $error("INVALID INSTRUCTION");
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endcase
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// write back
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@(posedge clk);
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$display("== WRITE REGISTERS ==");
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case (t_d_op)
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`INS_BRANCH, `INS_STORE, `INS_FENCE, `INS_ENVOP:;
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default: begin
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if (t_d_rd != 0) reg_int[t_d_rd] = t_e_result;
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end
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endcase
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// finish up
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reg_pc = t_e_branch ? t_e_address : reg_pc + 4;
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end
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endmodule |