33 lines
1.1 KiB
Systemverilog
33 lines
1.1 KiB
Systemverilog
`include "parts/hart.sv";
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`include "parts/pmmu.sv";
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`include "parts/rom.sv";
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`include "parts/ram.sv";
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module system();
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reg clock = 0; // its the clock
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reg wire_rd;
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reg wire_wr;
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reg[1:0] wire_size;
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reg[31:0] wire_addr;
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reg[31:0] wire_datar;
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reg[31:0] wire_dataw;
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reg wire_rom_rd;
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reg[31:0] wire_rom_addr;
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reg[31:0] wire_rom_datar;
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reg wire_ram_rd;
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reg wire_ram_wr;
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reg[1:0] wire_ram_size;
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reg[31:0] wire_ram_addr;
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reg[31:0] wire_ram_datar;
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reg[31:0] wire_ram_dataw;
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hart core(clock, wire_rd, wire_wr, wire_size, wire_addr, wire_datar, wire_dataw); // cpu thing
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rom#(.FILE("./build/kernel.mem")) rom(clock, wire_rom_rd, wire_rom_addr, wire_rom_datar);
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ram#(.SIZE('h1000)) ram(clock, wire_ram_rd, wire_ram_wr, wire_ram_size, wire_ram_addr, wire_ram_datar, wire_ram_dataw);
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pmmu pmmu(clock, wire_rd, wire_wr, wire_size, wire_addr, wire_datar, wire_dataw, wire_rom_rd, wire_rom_addr, wire_rom_datar, wire_ram_rd, wire_ram_wr, wire_ram_size, wire_ram_addr, wire_ram_datar, wire_ram_dataw);
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// run the clock
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always #5 clock = ~clock;
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endmodule; |