64 lines
1.5 KiB
Systemverilog
64 lines
1.5 KiB
Systemverilog
// System physical memory management unit, addresses are dword aligned
|
|
module pmmu(
|
|
clk,
|
|
rd, wr, size,
|
|
addr, datar, dataw,
|
|
|
|
rom_rd,
|
|
rom_addr, rom_datar,
|
|
|
|
ram_rd, ram_wr, ram_size,
|
|
ram_addr, ram_datar, ram_dataw
|
|
);
|
|
// INPUT SHIT
|
|
input clk;
|
|
input reg rd;
|
|
input reg wr;
|
|
input reg[1:0] size;
|
|
input reg[31:0] addr;
|
|
input reg[31:0] dataw;
|
|
output reg[31:0] datar;
|
|
|
|
// ROM
|
|
output reg rom_rd;
|
|
output reg[31:0] rom_addr;
|
|
input reg[31:0] rom_datar;
|
|
|
|
// RAM
|
|
output reg ram_rd;
|
|
output reg ram_wr;
|
|
output reg[1:0] ram_size;
|
|
output reg[31:0] ram_addr;
|
|
output reg[31:0] ram_dataw;
|
|
input reg[31:0] ram_datar;
|
|
|
|
always @(posedge clk) begin
|
|
rom_rd = 0;
|
|
ram_rd = 0;
|
|
ram_wr = 0;
|
|
|
|
if ((addr == 0 || addr > 0) && addr < 'h1000) begin
|
|
rom_addr = addr >> 2;
|
|
rom_rd = rd;
|
|
|
|
#1;
|
|
if (rd) datar = rom_datar;
|
|
|
|
rom_rd = 0;
|
|
end else if ((addr == 'h100000 || addr > 'h100000) && addr < 'h101000) begin
|
|
ram_addr = addr;
|
|
ram_rd = rd;
|
|
ram_wr = wr;
|
|
ram_size = size;
|
|
if (wr) ram_dataw = dataw;
|
|
|
|
#1;
|
|
if (rd) datar = ram_datar;
|
|
|
|
ram_wr = 0;
|
|
ram_rd = 0;
|
|
end else begin
|
|
$error("INVALID MEMORY ACCESS %08x", addr);
|
|
end
|
|
end
|
|
endmodule |