// RISC-V Read only memory
module rom(clk, rd, wr, addr, datar, dataw);
    input             clk;
    input  reg        rd;
    input  reg        wr; // wait why the fuck did i add a write pin
    input  reg [31:0] addr;
    output reg [31:0] datar;
    input  reg [31:0] dataw;

    always @(posedge clk) begin
        if (rd) begin
            case (addr >> 2)
                0:  datar = 0;
                1:  datar = 1;
                2:  datar = 2;
                3:  datar = 3;
                4:  datar = 4;
                5:  datar = 5;
                6:  datar = 6;
                7:  datar = 7;
                8:  datar = 8;
                9:  datar = 9;
                10: datar = 10;
                default: $error("INVALID MEMORY ACCESS"); 
            endcase
        end else begin 
            datar = 0;
        end
    end
endmodule