30 lines
861 B
Systemverilog
30 lines
861 B
Systemverilog
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// RISC-V Read only memory
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module rom(clk, rd, wr, addr, datar, dataw);
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input clk;
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input reg rd;
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input reg wr; // wait why the fuck did i add a write pin
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input reg [31:0] addr;
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output reg [31:0] datar;
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input reg [31:0] dataw;
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always @(posedge clk) begin
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if (rd) begin
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case (addr >> 2)
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0: datar = 0;
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1: datar = 1;
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2: datar = 2;
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3: datar = 3;
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4: datar = 4;
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5: datar = 5;
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6: datar = 6;
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7: datar = 7;
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8: datar = 8;
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9: datar = 9;
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10: datar = 10;
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default: $error("INVALID MEMORY ACCESS");
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endcase
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end else begin
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datar = 0;
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end
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end
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endmodule
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