factorio-riscv/board/parts/rom.sv

// RISC-V Read only memory
module rom(clk, rd, addr, datar);
    input             clk;
    input  reg        rd;
    input  reg [31:0] addr;
    output reg [31:0] datar;

    parameter SIZE = 'h100;
    parameter FILE = "";

    reg [31:0] data [0 : SIZE - 1];

    always @(posedge clk) begin
        if (rd) begin
            datar = data[addr];
        end else begin 
            datar = 0;
        end
    end

    initial begin
        $readmemh(FILE, data, 0, SIZE - 1);
    end
endmodule